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Microchip Technology /ATSAML11D16A /SCB /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (USERSETMPEND)USERSETMPEND 0 (VALUE_0)UNALIGN_TRP 0 (DIV_0_TRP)DIV_0_TRP 0 (BFHFNMIGN)BFHFNMIGN 0 (STKOFHFNMIGN)STKOFHFNMIGN 0 (DC)DC 0 (IC)IC 0 (BP)BP

UNALIGN_TRP=VALUE_0

Description

Configuration and Control Register

Fields

USERSETMPEND

User set main pending
UNALIGN_TRP

Unaligned trap

0 (VALUE_0): Do not trap unaligned halfword and word accesses

1 (VALUE_1): Trap unaligned halfword and word accesses
DIV_0_TRP

Divide by zero trap
BFHFNMIGN

BusFault in HardFault or NMI ignore
STKOFHFNMIGN

Stack overflow in HardFault and NMI ignore
DC

Data cache enable
IC

Instruction cache enable
BP

Branch prediction enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data